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T T DUC PR O A C EM E N TE O LE D R E P L OBS NDE E 5120 O MM HC5 Data Sheet R EC
HC-5509B
August 2003 FN2799.8
ITU CO/Loop Carrier SLIC
The HC-5509B telephone Subscriber Line Interface Circuit integrates most of the BORSCHT functions on a monolithic IC. The device is manufactured in a Dielectric Isolation (DI) process and is designed for use as a high voltage interface between the traditional telephone subscriber pair (Tip and Ring) and the low voltage filtering and coding/decoding functions of the line card. Together with a secondary protection diode bridge and "feed" resistors, the device will withstand 1000V lightning induced surges, in plastic packages. The SLIC also maintains specified transmission performance in the presence of externally induced longitudinal currents. The BORSCHT functions that the SLIC provides are: Battery Feed with Subscriber Loop Current Limiting * Overvoltage Protection * Ring Relay Driver * Supervisory Signaling Functions * Hybrid Functions (with External Op Amp) * Test (or Battery Reversal) Relay Driver In addition, the SLIC provides selective denial of power to subscriber loops, a programmable subscriber loop current limit from 20mA to 60mA, a thermal shutdown with an alarm output and line fault protection. Switch hook detection, ring trip detection and ground key detection functions are also incorporated in the SLIC device. The HC-5509B SLIC is ideally suited for line card designs in PBX and CO systems, replacing traditional transformer solutions.
Features
* DI Monolithic High Voltage Process * Compatible with Worldwide PBX and CO Performance Requirements * Controlled Supply of Battery Feed Current with Programmable Current Limit * Operates with 5V Positive Supply (VB+) * Internal Ring Relay Driver and a Utility Relay Driver * High Impedance Mode for Subscriber Loop * High Temperature Alarm Output * Low Power Consumption During Standby Functions * Switch Hook, Ground Key, and Ring Trip Detection * Selective Power Denial to Subscriber * Voice Path Active During Power Denial * On-Chip Op Amp for 2-Wire Impedance Matching
Applications
* Solid State Line Interface Circuit for PBX or Central Office Systems, Digital Loop Carrier Systems * Hotel/Motel Switching Systems * Direct Inward Dialing (DID) Trunks * Voice Messaging PBXs * High Voltage 2-Wire/4-Wire, 4-Wire/2-Wire Hybrid * Related Literature - AN9607, Impedance Matching Design Equations - AN9628, AC Voltage Gain - AN9608, Implementing Pulse Metering - AN549, The HC-5502S/4X Telephone Subscriber Line Interface Circuits (SLIC)
Part Number Information
PART NUMBER HC9P5509B-5 TEMP. RANGE (oC) 0 to 75 PACKAGE 28 Ld SOIC PKG. DWG. # M28.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HC-5509B
Absolute Maximum Ratings (Note 1)
Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 15V Maximum Supply Voltages (VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V (VB+)-(VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) JC (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . 72 N/A Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . .150oC Storage Temperature Range . . . . . . . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC (For SMD; SOIC - Lead Tips Only)
Operating Conditions
Operating Temperature Range HC-5509B-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC Relay Drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V Positive Power Supply (VB+) . . . . . . . . . . . . . . . . . . . . . . . . 5V 5% Negative Power Supply (VB-) . . . . . . . . . . . . . . . . . . . . -42V to -58V Loop Resistance (RL) . . . . . . . . . . . . . . . . .200 to 1750 (Note 2)
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Diode Count. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 x 120 Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connected Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. May Be Extended to 1900 With Application Circuit. 3. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are Over Operating Temperature Range, VB- = -48V, VB+ = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600 2-Wire Terminating Impedance TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER AC TRANSMISSION PARAMETERS RX Input Impedance TX Output Impedance 4-Wire Input Overload Level 2-Wire Return Loss SRL LO ERL SRL HI 2-Wire Longitudinal to Metallic Balance Off Hook 4-Wire Longitudinal Balance Off Hook Low Frequency Longitudinal Balance
300Hz to 3.4kHz (Note 4) 300Hz to 3.4kHz (Note 4) 300Hz to 3.4kHz RL = 1200 , 600 Reference Matched for 600 (Note 4)
1.5
100 -
20 -
k VPEAK
26 30 30 Per ANSI/IEEE STD 455-1976 (Note 4) 300Hz to 3400Hz 300Hz to 3400Hz (Note 4) R.E.A. Test Circuit ILINE = 40mA, TA = 25oC (Note 4) ILINE = 40mA, TA = 25oC (Note 4) 0dBm at 1kHz, Referenced 600 300Hz to 3400Hz (Note 4) Referenced to Absolute Level at 1kHz, 0dBm Referenced 600 Referenced to -10dBm (Note 4) +3 to -40dBm -40 to -50dBm -50 to -55dBm 58 50 -
35 40 40 63 55 0.05 0.05 0.02
-67 23 30 0.2 0.2 0.2 0.05
dB dB dB dB dB dBmp dBrnC mARMS dB dB dB dB
Longitudinal Current Capability Insertion Loss 2-Wire/4-Wire 4-Wire/2-Wire 4-Wire/4-Wire Frequency Response Level Linearity 2-Wire to 4-Wire and 4-Wire to 2-Wire
-
-
0.05 0.1 0.3
dB dB dB
2
HC-5509B
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are Over Operating Temperature Range, VB- = -48V, VB+ = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600 2-Wire Terminating Impedance (Continued) TEST CONDITIONS (Note 4) 300Hz to 3400Hz 300Hz to 3400Hz 300Hz to 3400Hz (Note 4) See Figure 1 Reference Level 0dBm at 600 300Hz to 3400Hz (Note 4) (Note 4) C-Message Psophometric 3kHz Flat Power Supply Rejection Ratio VB+ to 2-Wire VB+ to 4-Wire VB- to 2-Wire VB- to 4-Wire VB+ to 4-Wire VB- to 2-Wire VB- to 4-Wire VB- to 4-Wire Ring Sync Pulse Width DC PARAMETERS Loop Current Programming Limit Range Accuracy Loop Current During Power Denial Fault Currents TIP to Ground RING to Ground TIP and RING to Ground Switch Hook Detection Threshold Ground Key Detection Threshold Thermal ALARM Output Ring Trip Detection Threshold Ring Trip Detection Period Dial Pulse Distortion Relay Driver Outputs On Voltage VOL Off Leakage Current TTL/CMOS Logic Inputs (F0, F1, RS, TEST, PRI) Logic `0' VIL Logic `1' VIH Input Current (F0, F1, RS, TEST, PRI) 0V VIN 5V IOL (PR) = 60mA, IOL (RD) = 30mA VOH = 13.2V Safe Operating Die Temperature Exceeded VRING = 105VRMS, fRING = 20Hz RL = 200 20 10 140 2.0 3 30 60 90 12 10 10 100 0.1 0.2 10 60 5 15 160 150 0.5 0.5 100 0.8 5.5 100 mA % mA mA mA mA mA mA
oC
PARAMETER Absolute Delay 2-Wire/4-Wire 4-Wire/2-Wire 4-Wire/4-Wire Transhybrid Loss, THL Total Harmonic Distortion 2-Wire/4-Wire, 4-Wire/2-Wire, 4-Wire/4-Wire Idle Channel Noise 2-Wire and 4-Wire
MIN -
TYP 40 -
MAX 1 1 1.5 -52
UNITS s s s dB dB
20 20 20 20
29 29 29 29 25 25 -
5 -85 15 500
dBrnC dBmp dBrn dB dB dB dB dB dB dB dB s
(Note 4) 30Hz to 200Hz, RL = 600
(Note 4) 200Hz to 16kHz, RL = 600
30 30 20 20 50
mA ms ms V A V V A
3
HC-5509B
Electrical Specifications
Unless Otherwise Specified, Typical Parameters are at TA = 25oC, Min-Max Parameters are Over Operating Temperature Range, VB- = -48V, VB+ = 5V, AG = DG = BG = 0V. All AC Parameters are specified at 600 2-Wire Terminating Impedance (Continued) TEST CONDITIONS ILOAD = 800A ILOAD = 40A Relay Drivers Off VB+ = 5.25V, VB- = -58V, RLOOP = VB+ = 5.25V, VB- = -58V, RLOOP = MIN 2.7 TYP 0.1 200 5 10 1 3 1 MAX 0.5 6 UNITS V V mW mA mA
PARAMETER Logic Outputs Logic `0' VOL Logic `1' VOH Power Dissipation On Hook IB+ IBUNCOMMITTED OP AMP PARAMETERS Input Offset Voltage Input Offset Current Differential Input Resistance Output Voltage Swing Small Signal GBW NOTE: (Note 4) RL = 10k (Note 4)

-6
-
-
mV nA M VP-P MHz
4. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance.
Pin Descriptions
SOIC 1 2 3 4 SYMBOL AG (Note 5) VB+ C1 F1 DESCRIPTION Analog Ground - To be connected to zero potential. Serves as a reference for the transmit output and receive input terminals. Positive Voltage Source - most positive supply. Capacitor #C1 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function. Function Address #1 - A TTL and CMOS compatible input used with F0 function address line to externally select logic functions. The three selectable functions are mutually exclusive. See Truth Table. F1 should be toggled high after power is applied. Function Address #0 - A TTL and CMOS compatible input used with F1 function address line to externally select logic functions. The three selectable functions are mutually exclusive. See Truth Table. Ring Synchronization Input - A TTL - compatible clock input. The clock is arranged such that a positive pulse (50s 500s) occurs on the zero crossing of the ring voltage source, as it appears at the RFS terminal. For Tip side injected systems, the RS pulse should occur on the negative going zero crossing and for Ring injected systems, on the positive going zero crossing. This ensures that the ring delay activates and deactivates when the instantaneous ring voltage is near zero. If synchronization is not required, the pin should be tied to 5. Switch Hook Detection - An active low LS, TTL-compatible logic output. A line supervisory output. Ground Key Detection - An active low LS, TTL-compatible logic output. A line supervisory output. A TTL logic input. A low on this pin will set a latch and keep the SLIC in a power down mode until the proper F1, F0 state is set and will keep ALM low. See Truth Table. An LS TTL-compatible active low output which responds to the thermal detector circuit when a safe operating die temperature has been exceeded. When TST is forced low by an external control signal, ALM is latched low until the proper F1, F0 state and TST input is brought high. The ALM can be tied directly to the TST pin to power down the part when a thermal fault is detected and then reset with F0, F1. See Truth Table. It is possible to ignore transient thermal overload conditions in the SLIC by delaying the response to the TST pin from the ALM. Care must be exercised in attempting this as continued thermal overstress may reduced component life. Loop Current Limit - Voltage on this pin sets the short loop current limiting conditions using a resistive voltage divider. The analog output of the spare operational amplifier. The inverting analog input of the spare operational amplifier.
5 6
F0 RS
7 8 9 10
SHD GKD TST ALM
11 12 13
ILMT OUT1 -IN1
4
HC-5509B Pin Descriptions
SOIC 14 15 16 17 18 SYMBOL TIP RING RFS VRX C2 (Continued) DESCRIPTION An analog input connected to the TIP (more positive) side of the subscriber loop through a feed resistor and ring relay contact. Functions with the RING terminal to receive voice signals from the telephone and for loop monitoring purpose. An analog input connected to the RING (more negative) side of the subscriber loop through a feed resistor. Functions with the TIP terminal to receive voice signals from the telephone and for loop monitoring purposes. Ring Feed Sense - Senses RING side of the loop for Ground Key Detection. During Ring injected ringing the ring signal at this node is isolated from RF via the ring relay. For Tip injected ringing, the RF and RFS pins must be shorted. Receive Input, 4-Wire Side - A high impedance analog input. AC signals appearing at this input drive the Tip Feed and Ring Feed amplifiers differentially. Capacitor #C2 - An external capacitor to be connected between this terminal and ground. It prevents false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from power lines and other noise sources. This capacitor should be nonpolarized. Transmit Output, 4-Wire Side - A low impedance analog output which represents the differential voltage across TIP and RING. Transhybrid balancing must be performed beyond this output to completely implement 2-Wire to 4-Wire conversion. This output is referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is necessary. A TTL compatible input used to control PR. PRI active High = PR active low. An active low open collector output. Can be used to drive a Polarity Reversal Relay. Digital Ground - To be connected to zero potential. Serves as a reference for all digital inputs and outputs on the SLIC. Ring Relay Driver - An active low open collector output. Used to drive a relay that switches ringing signals onto the 2Wire line. Feedback input to the tip feed amplifier; may be used in conjunction with transmit output signal and the spare op amp to accommodate 2-Wire line impedance matching. Tip Feed - A low impedance analog output connected to the TIP terminal through a feed resistor. Ring Feed - A low impedance analog output connected to the RING terminal through a feed resistor. The battery voltage source. The most negative supply. Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal.
19
VTX
20 21 22 23 24 25 26 27 28 NOTE:
PRI PR DG (Note 5) RD VFB TF RF VBBG (Note 5)
5. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first.
5
HC-5509B Pinout
HC-5509B (SOIC) TOP VIEW
AG 1 VB+ C1 F1 F0 RS SHD GKD TST 2 3 4 5 6 7 8 9 28 BG 27 VB26 RF 25 TF 24 VFB 23 RD 22 DG 21 PR 20 PRI 19 VTX 18 C2 17 VRX 16 RFS 15 RING
TRUTH TABLE F1 0 0 1 1 1 F0 0 1 0 0 1 ACTION Normal Loop Feed RD Active (Ringing) Power Down Latch RESET Power On RESET Loop Power Denial Active
ALM 10 ILMT 11 OUT 1 12 -IN 1 13 TIP 14
Functional Diagram
SOIC
R R 2R R/2 2R R R TIP 14 R R 4.5K 100K RING 15 100K 100K RFS 16 100K 4.5K 90K 25K 2R
VRX 17
OUT 1 12
-IN 1 13
VFB 24
VTX 19
VB+ 2
DG 22
AG 1 28 BG
TF
25
TF +
-
+ RF1
OP AMP
BIAS NETWORK
27 4 5
VBF1 F0 RS TST
-
THERM LTD
TSD
IIL LOGIC INTERFACE
TA + 2R
SHD
SH
6 9 20 21
PRI PR
LA + 25K
90K
RTD GKD
GK
23 RD 7 8 SHD GKD ALM
FAULT DET
RFC 90K 26 R = 108k C1 10
RF
RF
+ 3
90K
VB/2 REF C2
18
GM +
-
RF2 11 ILMT
6
HC-5509B Overvoltage Protection and Longitudinal Current Protection
The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. High voltage surge conditions are as specified in Table 1. The SLIC will withstand longitudinal currents up to a maximum or 30mARMS , 15mARMS per leg, without any performance degradation.
PARAMETER Longitudinal Surge Metallic Surge T/GND, R/GND 50/60Hz Current T/GND, R/GND 11 Cycles, 700 (Plastic) Limited to 10ARMS VRMS TABLE 1. TEST CONDITION 10s Rise/ 1000s Fall 10s Rise/ 1000s Fall 10s Rise/ 1000s Fall PERFORMANCE (MAX) 1000 (Plastic) 1000 (Plastic) 1000 (Plastic) UNITS VPEAK VPEAK VPEAK
Logic Diagram
RS
TTL TO I2L
RELAY DRIVER
RD
TTL TO I2L F0 I2L TO TTL GKD GK I2L TO TTL SHD THERMAL SHUT DOWN I2L TO TTL ALM F1
TTL TO I2L
PD SH
TTL TO I2L TEST
THERMAL SHUT DOWN LATCH
TO BIAS NETWORK
INJ A B C KEY A B C
7
HC-5509B Typical Applications
5V 5V K1 RS1 CS1 K2 SHD GKD PRI RS TEST F1 ALARM F0 RD PR RB1 SECONDARY PROTECTION (NOTE 8) VBC5 PRIMARY PROTECTION KIB RS2 CS2 RFS RB4 150VPEAK (MAX) VRING OUT1 TO HYBRID BALANCE NETWORK BG C2 DG AG V B+ C 1 RF SLIC HC-5509B VTX KRF -IN1 KZ0 RB2 TIP ILIMIT VRX+ RL1 VFB CAC FROM PCM FILTER/CODER RL2 SYSTEM CONTROLLER
TIP
K1A
RB3 RING PTC
RING VB-
Z1
C3
C4 5V
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C1 = 0.5F, 30V. C2 = 1.0F 10%, 20V (for other values of C2 , refer to AN9667). C3 = 0.01F, 100V, 20%. C4 = 0.01F, 100V, 20%. C5 = 0.01F, 100V, 20%. CAC = 0.5F, 20V. KZ0 = 60k, (Z0 = 600, K = Scaling Factor = 100). RL1 , RL2 ; Current Limit Setting Resistors: RL1 + RL2 > 90k offset. ILIMIT = (0.6) (RL1 + RL2)/(200 x RL2), RL1 typically 100k. KRF = 20k, RF = 2(RB2 + RB4), K = Scaling Factor = 100). RB1 = RB2 = RB3 = RB4 = 50 (1% absolute, matching requirements covered in a Tech Brief). RS1 = RS2 = 1k , typically. CS1 = CS2 = 0.1F, 200V typically, depending on VRing and line length. Z1 = 150V to 200V transient protector. PTC used as ring generator ballast.
8
HC-5509B Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 17.70 7.40 MAX 2.65 0.30 0.51 0.32 18.10 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.6969 0.2914
MAX 0.1043 0.0118 0.0200 0.0125 0.7125 0.2992
B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.01 0.016 28 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 28 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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